30 lines
656 B
Systemverilog
30 lines
656 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer i;
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integer j;
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always @(i, j) $display("[%0t] B %0d %0d", $time, i, j);
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// See issue #4237
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initial begin
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for (i = 1; i < 3; i = i + 1) begin
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$display("");
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for (j = 6; j < 8; j = j + 1) begin
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$display("[%0t] A %0d %0d", $time, i, j);
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#1;
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$display("[%0t] C %0d %0d", $time, i, j);
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end
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#9;
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end
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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