32 lines
781 B
Systemverilog
32 lines
781 B
Systemverilog
// DESCRIPTION: Verilator: Confirm x randomization stability
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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localparam logic [1:0][7:0] foo_unpacked[2:0] = '{"12", "34", "56"};
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localparam logic [2:0][1:0][7:0] foo_packed = '{"12", "34", "56"};
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sub #(.foos({foo_unpacked[0], foo_unpacked[1], foo_unpacked[2]})) the_unpacked_sub ();
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sub #(.foos({foo_packed[0], foo_packed[1], foo_packed[2]})) the_packed_sub ();
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endmodule
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module sub #(
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parameter logic [2:0][1:0][7:0] foos
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);
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initial begin
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if (foos != "563412") $stop;
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end
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endmodule
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