31 lines
902 B
Systemverilog
31 lines
902 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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// verilog_format: off
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localparam string REGS [0:31]
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= '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
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"s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
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"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6",
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"fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
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"ft10", "ft11"};
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// verilog_format: on
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function string disasm32(logic [4:0] op);
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return $sformatf("lui %s", REGS[op]);
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endfunction
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endpackage
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module t ( /*AUTOARG*/
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// Inputs
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op
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);
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import pkg::*;
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input [4:0] op;
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always_comb begin
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$display("OP: 0x%08x: %s", op, disasm32(op));
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end
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endmodule
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