verilator/test_regress/t/t_unoptflat_simple_bad.out

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%Warning-UNOPTFLAT: t/t_unoptflat_simple.v:15:14: Signal unoptimizable: Circular combinational logic: 't.x'
15 | wire [1:0] x = {x[0], clk};
| ^
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
t/t_unoptflat_simple.v:15:14: Example path: t.x
t/t_unoptflat_simple.v:15:16: Example path: ASSIGNW
t/t_unoptflat_simple.v:15:14: Example path: t.x
%Error: Exiting due to