79 lines
1.2 KiB
Systemverilog
79 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Simple test of unoptflat
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//
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// Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping
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// through 2 sub-modules.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [2:0] x;
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test1 test1i (
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.clk(clk),
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.xvecin(x[1:0]),
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.xvecout(x[2:1])
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);
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test2 test2i (
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.clk(clk),
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.xvecin(x[2:1]),
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.xvecout(x[1:0])
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);
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always @(posedge clk or negedge clk) begin
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`ifdef TEST_VERBOSE
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$write("x = %x\n", x);
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`endif
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if (x[1] != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule // t
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module test1 ( /*AUTOARG*/
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// Inputs
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clk,
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xvecin,
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// Outputs
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xvecout
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);
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input clk;
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input wire [1:0] xvecin;
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output wire [1:0] xvecout;
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assign xvecout = {xvecin[0], clk};
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endmodule // test
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module test2 ( /*AUTOARG*/
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// Inputs
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clk,
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xvecin,
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// Outputs
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xvecout
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);
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input clk;
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input wire [1:0] xvecin;
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output wire [1:0] xvecout;
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assign xvecout = {clk, xvecin[1]};
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endmodule // test
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