36 lines
652 B
Systemverilog
36 lines
652 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Jue Xu
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// SPDX-License-Identifier: CC0-1.0
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// bug630
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module t (
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clk,
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out
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);
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input clk;
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output out;
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reg a;
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reg b;
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typedef struct packed {
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logic config_a;
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logic config_b;
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} param_t;
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// verilator lint_off UNOPTFLAT
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param_t conf[1:2];
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// verilator lint_on UNOPTFLAT
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always @(posedge clk) begin
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conf[2].config_b <= a;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge conf[2].config_b) begin
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a = conf[2].config_a;
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end
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endmodule
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