54 lines
911 B
Systemverilog
54 lines
911 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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wire o_n;
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wire o_0;
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wire o_1;
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// verilator lint_off PINMISSING
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sub_0 sub_0 (.o_0);
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sub_1 sub_1 (.o_1);
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sub_n sub_n (.o_n);
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// verilator lint_on PINMISSING
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always @(posedge clk) begin
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if (o_0 !== 1'b0) $stop;
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if (o_1 !== 1'b1) $stop;
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//4-state if (o_n !== 1'bz) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`unconnected_drive pull0
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module sub_0 (
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input i,
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output wire o_0
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);
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assign o_0 = i;
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endmodule
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`unconnected_drive pull1
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module sub_1 (
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input i,
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output wire o_1
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);
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assign o_1 = i;
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endmodule
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`nounconnected_drive
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module sub_n (
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input i,
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output wire o_n
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);
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assign o_n = i;
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endmodule
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