88 lines
1.7 KiB
Systemverilog
88 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Unsupported tristate construct error
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//
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// This is a compile only regression test of tristate handling for bug514
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Rob Stoddard
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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out,
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// Inputs
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data,
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up_down,
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clk,
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reset
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);
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//----------Output Ports--------------
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output [7:0] out;
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//------------Input Ports--------------
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//input [7:0] data ;
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input [7:0] data;
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input up_down, clk, reset;
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//------------Internal Variables--------
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reg [7:0] out;
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logic [7:0] q_out;
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//-------------Code Starts Here-------
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always @(posedge clk)
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if (reset) begin // active high reset
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out <= 8'b0;
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end
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else if (up_down) begin
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out <= out + 1;
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end
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else begin
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out <= q_out;
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end
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// verilator lint_off PINMISSING
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sub_mod sub_mod (
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.clk(clk),
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.data(data),
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.reset(reset),
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.q(q_out)
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);
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// verilator lint_on PINMISSING
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endmodule
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module sub_mod ( /*AUTOARG*/
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// Outputs
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q,
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test_out,
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// Inouts
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test_inout,
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// Inputs
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data,
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clk,
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reset
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);
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//-----------Input Ports---------------
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input [7:0] data /*verilator public*/;
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input clk, reset;
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inout test_inout; // Get rid of this, the problem goes away.
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//-----------Output Ports---------------
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output [7:0] q;
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output test_out; // Not assigned, no problem.
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logic [7:0] que;
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// Uncomment this line, the error goes away.
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//assign test_inout = que;
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assign q = que;
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always @(posedge clk)
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if (~reset) begin
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que <= 8'b0;
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end
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else begin
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que <= data;
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end
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endmodule
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