129 lines
3.6 KiB
Systemverilog
129 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [3:0] drv_a = crc[3:0];
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wire [3:0] drv_b = crc[7:4];
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wire [3:0] drv_e = crc[19:16];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [8:0] match1; // From test1 of Test1.v
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wire [8:0] match2; // From test2 of Test2.v
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// End of automatics
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Test1 test1 ( /*AUTOINST*/
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// Outputs
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.match1(match1[8:0]),
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// Inputs
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.drv_a(drv_a[3:0]),
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.drv_e(drv_e[3:0])
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);
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Test2 test2 ( /*AUTOINST*/
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// Outputs
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.match2(match2[8:0]),
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// Inputs
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.drv_a(drv_a[3:0]),
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.drv_e(drv_e[3:0])
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {39'h0, match2, 7'h0, match1};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n", $time, cyc, crc, match1, match2,
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drv_e, drv_a, drv_b);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test1 (
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input wire [3:0] drv_a,
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input wire [3:0] drv_e,
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output wire [8:0] match1
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);
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wire [2:1] drv_all;
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bufif1 bufa[2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
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`ifdef VERILATOR
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// At present Verilator only allows comparisons with Zs
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assign match1[0] = (drv_a[2:1] == 2'b00 && drv_e[2:1] == 2'b11);
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assign match1[1] = (drv_a[2:1] == 2'b01 && drv_e[2:1] == 2'b11);
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assign match1[2] = (drv_a[2:1] == 2'b10 && drv_e[2:1] == 2'b11);
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assign match1[3] = (drv_a[2:1] == 2'b11 && drv_e[2:1] == 2'b11);
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`else
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assign match1[0] = drv_all === 2'b00;
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assign match1[1] = drv_all === 2'b01;
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assign match1[2] = drv_all === 2'b10;
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assign match1[3] = drv_all === 2'b11;
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`endif
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assign match1[4] = drv_all === 2'bz0;
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assign match1[5] = drv_all === 2'bz1;
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assign match1[6] = drv_all === 2'bzz;
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assign match1[7] = drv_all === 2'b0z;
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assign match1[8] = drv_all === 2'b1z;
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endmodule
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module Test2 (
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input wire [3:0] drv_a,
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input wire [3:0] drv_e,
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output wire [8:0] match2
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);
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wire [2:1] drv_all;
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bufif1 bufa[2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
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`ifdef VERILATOR
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assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1] != 2'b11);
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assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1] != 2'b11);
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assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1] != 2'b11);
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assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1] != 2'b11);
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`else
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assign match2[0] = drv_all !== 2'b00;
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assign match2[1] = drv_all !== 2'b01;
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assign match2[2] = drv_all !== 2'b10;
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assign match2[3] = drv_all !== 2'b11;
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`endif
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assign match2[4] = drv_all !== 2'bz0;
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assign match2[5] = drv_all !== 2'bz1;
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assign match2[6] = drv_all !== 2'bzz;
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assign match2[7] = drv_all !== 2'b0z;
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assign match2[8] = drv_all !== 2'b1z;
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endmodule
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