28 lines
431 B
Systemverilog
28 lines
431 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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o,
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// Inputs
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i
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);
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input i;
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output o;
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sub sub (
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i,
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o
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);
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endmodule
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module sub (
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input i,
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output o
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);
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assign o = (i === 1'bz) ? 1'b0 : i;
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endmodule
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