28 lines
463 B
Systemverilog
28 lines
463 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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integer c_trace_on;
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real r;
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sub sub ();
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always @(posedge clk) begin
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if (cyc != 0) begin
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r <= r + 0.1;
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end
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end
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endmodule
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module sub;
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integer inside_sub_a = 2;
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endmodule
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