51 lines
843 B
Systemverilog
51 lines
843 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t;
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localparam CLK_PERIOD = 10;
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localparam CLK_HALF_PERIOD = CLK_PERIOD / 2;
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logic rst;
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logic clk;
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logic a;
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logic b;
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logic c;
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logic d;
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event ev;
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initial begin
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars;
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forever clk = #CLK_HALF_PERIOD ~clk;
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end
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always begin
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rst = 1;
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clk = 0;
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a = 0;
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c = 0;
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b = ~b;
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d = 0;
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fork
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#(10 * CLK_PERIOD) b = 0;
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join_none
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while (b) begin
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c = ~c;
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->ev;
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#CLK_PERIOD;
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end
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$write("[%0t] Done\n", $time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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