80 lines
1.6 KiB
Systemverilog
80 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface counter_if;
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logic valid;
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logic [3:0] value;
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logic reset;
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modport counter_mp(input reset, output valid, output value);
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modport core_mp(output reset, input valid, input value);
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endinterface
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interface counter_if2 (
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counter_if.counter_mp c_mp
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);
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task automatic reset();
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c_mp.valid = '0;
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c_mp.value = '0;
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endtask
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task automatic init();
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c_mp.valid = '0;
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c_mp.value = '1;
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endtask
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endinterface
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interface counter_if3 (
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counter_if.counter_mp c_mp
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);
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task automatic reset();
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c_mp.valid = '0;
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c_mp.value = '0;
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endtask
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task automatic init();
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c_mp.valid = '1;
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c_mp.value = 4'ha;
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endtask
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endinterface
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module t (
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input clk
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);
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integer cyc = 1;
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counter_if c5_data ();
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counter_if c6_data ();
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counter_if2 cif2 (c5_data.counter_mp);
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counter_if3 cif3 (c6_data.counter_mp);
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initial begin
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cif2.reset();
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cif3.reset();
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc < 2) begin
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if (c5_data.valid != '0) $stop;
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if (c5_data.value != '0) $stop;
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if (c6_data.valid != '0) $stop;
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if (c6_data.value != '0) $stop;
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end
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if (cyc == 2) begin
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cif2.init();
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cif3.init();
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end
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if (cyc == 20) begin
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if (c5_data.valid != '0) $stop;
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if (c5_data.value != '1) $stop;
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if (c6_data.valid != '1) $stop;
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if (c6_data.value != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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