26 lines
473 B
Systemverilog
26 lines
473 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input reset_l
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);
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sub_top u0_sub_top (
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.clk(clk),
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.reset_l(reset_l)
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);
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sub_top u1_sub_top (
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.clk(clk),
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.reset_l(reset_l)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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