45 lines
780 B
Systemverilog
45 lines
780 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk = 1;
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logic clk_inv;
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event a;
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event e;
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// This $c is required to prevent inlining clk_inv as ~clk
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assign clk_inv = $c(1) & ~clk;
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// This is needed to provide right order of resumption in scheduler
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initial begin
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@a;
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@(posedge clk_inv);
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@e;
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end
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initial begin
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forever begin
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@(posedge clk_inv) begin
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clk = 1;
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->e;
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@e;
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end
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end
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end
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initial begin
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@a;
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@e;
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if (clk_inv != 0) $stop;
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$finish;
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end
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initial begin
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#1;
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->a;
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clk = 0;
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#2 $stop;
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end
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endmodule
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