145 lines
3.2 KiB
Systemverilog
145 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
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//
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// This code instantiates and runs a simple CPU written in System Verilog.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
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module t (
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input clk
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);
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/*AUTOWIRE*/
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// **************************************************************************
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// Regs and Wires
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// **************************************************************************
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reg rst;
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integer rst_count;
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integer clk_count;
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testbench testbench_i ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.rst(rst)
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);
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// **************************************************************************
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// Reset Generation
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// **************************************************************************
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initial begin
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rst = 1'b1;
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rst_count = 0;
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end
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always @(posedge clk) begin
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if (rst_count < 2) begin
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rst_count++;
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end
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else begin
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rst = 1'b0;
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end
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end
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// **************************************************************************
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// Drive simulation for 500 clock cycles
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// **************************************************************************
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initial begin
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`ifdef TEST_VERBOSE
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$display("[testbench] - Start of simulation ----------------------- ");
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`endif
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clk_count = 0;
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end
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always @(posedge clk) begin
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if (90 == clk_count) begin
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$finish();
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end
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else begin
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clk_count++;
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end
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end
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final begin
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`ifdef TEST_VERBOSE
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$display("[testbench] - End of simulation ------------------------- ");
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`endif
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$write("*-* All Finished *-*\n");
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end
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endmodule
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module testbench ( /*AUTOARG*/
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// Inputs
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clk,
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rst
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);
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input clk;
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input rst;
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// **************************************************************************
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// Local parameters
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// **************************************************************************
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localparam NUMPADS = $size(pinout);
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// **************************************************************************
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// Regs and Wires
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// **************************************************************************
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// **** Pinout ****
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`ifdef VERILATOR // see t_tri_array
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wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
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`else
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wire pad[1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
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`endif
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// **************************************************************************
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// Regs and Wires, Automatics
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// **************************************************************************
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/*AUTOWIRE*/
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// **************************************************************************
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// Includes (Testbench extensions)
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// **************************************************************************
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// N/A
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// **************************************************************************
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// Chip Instance
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// **************************************************************************
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chip i_chip (
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/*AUTOINST*/
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// Inouts
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.pad(pad[NUMPADS:1]),
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// Inputs
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.clk(clk),
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.rst(rst)
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);
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endmodule // test
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// Local Variables:
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// verilog-library-directories:("." "t_sv_cpu_code")
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// End:
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