27 lines
566 B
Systemverilog
27 lines
566 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2022 Jomit626
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// SPDX-License-Identifier: CC0-1.0
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`ifndef WIDE_WIDTH
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`define WIDE_WIDTH 128
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`endif
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module t;
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typedef struct {bit [`WIDE_WIDTH-1:0] data;} wide_t;
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logic [`WIDE_WIDTH-1:0] ldata;
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wide_t wide_0;
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initial begin
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wide_0.data = `WIDE_WIDTH'hda7ada7a;
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ldata = wide_0.data;
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if (ldata != `WIDE_WIDTH'hda7ada7a) $stop();
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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