43 lines
814 B
Systemverilog
43 lines
814 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef enum logic [1:0] {
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ZERO,
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ONE
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} enum_t;
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typedef struct {bit a;} struct_unpacked_t;
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typedef union {bit a;} union_unpacked_t;
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class Cls;
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bit a;
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endclass
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// IEEE 1800-2023 7.2.1
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typedef struct packed {
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real r; // BAD
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// verilator lint_off SHORTREAL
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shortreal sr; // BAD
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realtime rt; // BAD
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chandle ch; // BAD
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string s; // BAD
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event e; // BAD
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struct_unpacked_t sp; // BAD
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union_unpacked_t up; // BAD
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int uarray[2]; // BAD
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Cls c; // BAd
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} illegal_t;
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illegal_t s;
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initial begin
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$stop;
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end
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endmodule
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