61 lines
1.2 KiB
Systemverilog
61 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "VAMS-2.3"
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module t (
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input clk
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);
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integer cyc = 0;
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real vin[0:1] /*verilator split_var*/;
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wreal vout[0:1] /*verilator split_var*/;
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swap i_swap (
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.in0(vin[0]),
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.in1(vin[1]),
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.out0(vout[0]),
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.out1(vout[1])
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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vin[0] = 1.0;
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vin[1] = 2.0;
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end
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else if (cyc == 2) begin
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vin[0] = 3.0;
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vin[1] = 4.0;
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end
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else if (cyc == 3) begin
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if (vout[0] == vin[1] && vout[1] == vin[0]) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Mismatch %f %f\n", vout[0], vout[1]);
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$stop;
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end
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end
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end
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endmodule
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module swap (
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input wreal in0,
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in1,
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output wreal out0,
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out1
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);
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wreal tmp[0:1] /* verilator split_var*/;
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assign tmp[0] = in0;
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assign tmp[1] = in1;
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assign out0 = tmp[1];
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assign out1 = tmp[0];
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endmodule
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