40 lines
868 B
Systemverilog
40 lines
868 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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dataout,
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// Inputs
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clk,
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sel,
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d0,
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d1
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);
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input clk;
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input sel;
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logic [7:0] data[1:0][3:0];
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input [7:0] d0, d1;
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output wire [8*2*4-1:0] dataout;
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always_comb begin
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for (integer j = 0; j <= 1; j++) begin
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if (sel) data[j] = '{d0, d1, 8'h00, 8'h00};
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else data[j] = '{8'h00, 8'h00, 8'h00, 8'h00};
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end
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for (integer j = 0; j <= 1; j++) begin
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data[j] = sel ? '{d0, d1, 8'h00, 8'h00} : '{8'h00, 8'h00, 8'h00, 8'h00};
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end
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end
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assign dataout = {
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data[0][0], data[0][1], data[0][2], data[0][3], data[1][0], data[1][1], data[1][2], data[1][3]
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};
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endmodule
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