28 lines
533 B
Systemverilog
28 lines
533 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module serial_adder (
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input cin,
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output cout
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);
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localparam WIDTH = 8;
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wire [WIDTH:0] c;
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generate
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for (genvar i = 0; i < WIDTH; i++) full_adder fa (c[i+1]);
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endgenerate
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assign c[0] = cin;
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assign cout = c[WIDTH+1]; // intentional out-of-range
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endmodule
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module full_adder (
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output cout
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);
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endmodule
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