28 lines
489 B
Systemverilog
28 lines
489 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module x;
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bit val = 0;
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bit ok = 0;
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initial
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#1 begin
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val = 1;
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@(val);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial
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@(posedge val) begin
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val = 0;
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ok = 1;
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@(edge val);
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$stop;
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end
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initial #10 $stop;
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endmodule
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