22 lines
650 B
Systemverilog
22 lines
650 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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initial begin
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automatic integer r = $random;
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integer ex;
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if ($value$plusargs("SEED=%x", ex) !== 1) $stop;
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`checkh(r, ex);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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