93 lines
1.5 KiB
Systemverilog
93 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Justin Yao Du
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// SPDX-License-Identifier: CC0-1.0
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typedef logic [7:0] Word;
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typedef logic [255:0] BigItem;
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module shuffler (
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input logic clk,
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input logic reset_l,
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output logic odd,
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output logic [255:0][7:0] shuffle
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);
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Word ctr;
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assign odd = ctr[0];
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always_ff @(posedge clk) begin
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if (!reset_l) begin
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ctr <= 0;
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end
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else begin
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ctr <= ctr + 1;
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end
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end
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for (genvar i = 0; i < 256; i++)
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always_comb begin
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shuffle[i] = Word'(i) - ctr;
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end
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for (genvar i = 0; i < 256; i++) begin
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assert property (@(posedge clk) shuffle[ctr+Word'(i)] == i);
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end
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endmodule
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interface big_port ();
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BigItem big;
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function automatic BigItem get_big();
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return big;
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endfunction
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modport reader(import get_big);
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endinterface
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module foo (
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input clk,
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input reset_l,
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big_port.reader big
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);
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logic odd;
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Word [255 : 0] shuffle;
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shuffler fifo (
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.clk,
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.reset_l,
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.odd,
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.shuffle
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);
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BigItem bigs[256];
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for (genvar i = 0; i < 256; i++)
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always_comb begin
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bigs[i] = odd ? big.get_big() : 0;
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end
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endmodule
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module t ( /*AUTOARG*/
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// Inputs
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clk,
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reset_l
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);
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input clk;
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input reset_l;
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big_port big ();
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foo foo (
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.clk,
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.reset_l,
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.big
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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