44 lines
888 B
Systemverilog
44 lines
888 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk1 = 1'b0;
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bit clk2 = 1'b0;
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always #5 clk1 = ~clk1;
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always #10 clk2 = ~clk2;
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int iarray[63:0];
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int oarray1[63:0];
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int oarray2[63:0];
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initial begin
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for (int i = 0; i < 64; i = i + 1) begin
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iarray[i] = i;
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end
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#100;
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for (int i = 0; i < 64; i = i + 1) begin
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$display("%d %d %d", i, oarray1[i], oarray2[i]);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk1) begin
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for (int i = 0; i < 64; i = i + 1) begin
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oarray1[i] = iarray[i];
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end
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end
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always @(posedge clk2) begin
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for (int i = 0; i < 64; i = i + 1) begin
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oarray2[i] = iarray[i];
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end
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end
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endmodule
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