46 lines
1.6 KiB
Systemverilog
46 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
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// verilog_format: on
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// Soft constraint relaxation must preserve the maximum compatible set.
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// When soft[1] conflicts with soft[2], a correct algorithm should still
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// keep soft[0] if it is compatible with soft[2].
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//
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// soft[0]: b > 100 (low priority, COMPATIBLE with soft[2])
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// soft[1]: a == 30 (mid priority, CONFLICTS with soft[2])
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// soft[2]: a == 80 (high priority, should win over soft[1])
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//
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// Correct result: a == 80, b > 100 (soft[0] and soft[2] both kept)
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// Bug result: a == 80, b unconstrained (soft[0] wrongly dropped)
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class SoftRelax;
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rand bit [7:0] a;
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rand bit [7:0] b;
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constraint c_hard { a < 8'd200; b < 8'd200; }
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constraint c_soft0 { soft b > 8'd100; }
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constraint c_soft1 { soft a == 8'd30; }
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constraint c_soft2 { soft a == 8'd80; }
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endclass
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module t;
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initial begin
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SoftRelax obj;
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obj = new;
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repeat (20) begin
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`checkd(obj.randomize(), 1)
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`checkd(obj.a, 8'd80)
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`check_range(obj.b, 8'd101, 8'd199)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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