25 lines
618 B
Systemverilog
25 lines
618 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int m_dyn_arr[];
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rand int m_unp_arr[10];
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rand struct {int y;} m_struct;
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static rand int m_static;
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endclass
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module t;
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initial begin
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automatic Packet p = new;
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p.m_dyn_arr[0].rand_mode(0);
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p.m_unp_arr[0].rand_mode(0);
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p.m_struct.y.rand_mode(0);
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p.m_static.rand_mode(0);
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$display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode());
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p.rand_mode(0);
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end
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endmodule
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