42 lines
1.0 KiB
Systemverilog
42 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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class item;
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rand int unsigned arr[4];
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rand int unsigned wgt_zero;
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rand int unsigned wgt_nonzero;
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constraint wgt_c {
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wgt_zero inside {[1:10]};
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wgt_nonzero inside {[1:10]};
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}
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constraint dist_foreach_c {
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foreach (arr[i]) {
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arr[i] dist {0 :/ wgt_zero, [1:15] :/ wgt_nonzero};
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}
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}
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endclass
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initial begin
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static item it = new;
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repeat (20) begin
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`checkd(it.randomize(), 1);
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foreach (it.arr[i]) begin
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`checkd(it.arr[i] <= 32'd15, 1);
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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