83 lines
1.6 KiB
Systemverilog
83 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface secret_intf ();
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logic secret_a;
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integer secret_b;
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endinterface
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module t (
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input clk
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);
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secret_sub secret_inst (.*);
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secret_other secret_inst2 (.*);
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endmodule
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module secret_sub (
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input clk
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);
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// verilator no_inline_module
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typedef struct {
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integer secret_field;
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integer secret_field_r;
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} secret_st;
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int secret_cyc;
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real secret_cyc_r;
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integer secret_o;
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real secret_r;
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secret_st secret_pair;
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export "DPI-C" task dpix_a_task;
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task dpix_a_task(input int i, output int o);
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o = i + 1;
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endtask
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import "DPI-C" context task dpii_a_task(
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input int i,
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output int o
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);
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export "DPI-C" function dpix_a_func;
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function int dpix_a_func(input int i);
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return i + 2;
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endfunction
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import "DPI-C" context function int dpii_a_func(input int i);
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// Test loop
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always @(posedge clk) begin
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secret_pair.secret_field += 1;
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secret_pair.secret_field_r += 2;
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secret_cyc_r = $itor(secret_cyc) / 10.0 - 5.0;
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secret_cyc <= dpii_a_func(secret_cyc);
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secret_r += 1.0 + $cos(secret_cyc_r);
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dpix_a_task(secret_cyc, secret_o);
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if (secret_cyc == 90) begin
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$write("*-* All Finished *-*\n");
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end
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end
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endmodule
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module secret_other (
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input clk
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);
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int secret_cyc;
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always @(posedge clk) begin
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secret_cyc <= secret_cyc + 1;
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if (secret_cyc == 99) begin
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$finish;
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end
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end
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secret_intf secret_interface ();
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endmodule
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