58 lines
1.2 KiB
Systemverilog
58 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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Test test ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.cyc(cyc[31:0])
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (
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input clk,
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input [31:0] cyc
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);
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`ifdef FAIL_ASSERT_1
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assert property (@(posedge clk) cyc == 3)
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else $display("cyc != 3, cyc == %0d", cyc);
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assume property (@(posedge clk) cyc == 3)
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else $display("cyc != 3, cyc == %0d", cyc);
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`endif
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`ifdef FAIL_ASSERT_2
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assert property (@(posedge clk) cyc != 3);
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assume property (@(posedge clk) cyc != 3);
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`endif
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assert property (@(posedge clk) cyc < 100);
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assume property (@(posedge clk) cyc < 100);
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restrict property (@(posedge clk) cyc == 1); // Ignored in simulators
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// Unclocked is not supported:
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// assert property (cyc != 6);
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endmodule
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