23 lines
387 B
Systemverilog
23 lines
387 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define CHECK text \
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multiline
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Hello in t_preproc_psl.v
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`ifdef NEVER
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not
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`else
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yes
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`endif
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Multi `CHECK line
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// Did we end up right?
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Line: `__LINE__
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