49 lines
705 B
Systemverilog
49 lines
705 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [3:0] a, b;
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Test1 t1 (
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clk,
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a,
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b
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);
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initial begin
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a = 0;
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b = 0;
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end
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always @(posedge clk) begin
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a <= a + 1;
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b = b + 1;
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if (b >= 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test1 (
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clk,
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a,
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b
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);
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input clk;
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input [3:0] a, b;
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always @(posedge clk) begin
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if (a < 9) $strobe("%0d == %0d, %0d == %0d", a, b, $past(a), $past(b));
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end
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endmodule
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