152 lines
3.9 KiB
Systemverilog
152 lines
3.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Peter Monsson
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// SPDX-License-Identifier: Unlicense
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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wire [31:0] in = cyc;
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Test test ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.in(in[31:0])
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);
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Test2 test2 ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.in(in[31:0])
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);
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Test3 test3 ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.in(in[31:0])
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Inputs
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clk,
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in
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);
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input clk;
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input [31:0] in;
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bit [31:0] dly0 = 0;
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bit [31:0] dly1 = 0;
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bit [31:0] dly2 = 0;
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// If called in an assertion, sequence, or property, the appropriate clocking event.
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// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
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// Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used.
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// Otherwise, if called in a procedure, the inferred clock
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// Otherwise, default clocking
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= dly0;
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dly2 <= dly1;
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// In clock expression
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$write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0));
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if ($rose(dly0[4])) $stop;
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if ($fell(dly0[4])) $stop;
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if (!$stable(dly0[4])) $stop;
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if ($changed(dly0[4])) $stop;
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end
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assert property (@(posedge clk) $rose(dly0) || dly0 % 2 == 0 || dly2 < 3);
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assert property (@(posedge clk) $fell(dly1) || dly1 % 2 == 1 || dly2 < 3);
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assert property (@(posedge clk) !$stable(dly2) || dly2 < 3);
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assert property (@(posedge clk) $changed(dly2) || dly2 < 3);
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global clocking @(posedge clk);
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endclocking
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always @($global_clock) $display("gc in=%0d", in);
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//
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assert property (@(posedge clk) $rose(dly0, $global_clock) || dly0 % 2 == 0 || dly2 < 3);
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assert property (@(posedge clk) $fell(dly1, $global_clock) || dly1 % 2 == 1 || dly2 < 3);
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assert property (@(posedge clk) !$stable(dly2, $global_clock) || dly2 < 3);
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assert property (@(posedge clk) $changed(dly2, $global_clock) || dly2 < 3);
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//
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assert property (@(posedge clk) $rose_gclk(dly0) || dly0 % 2 == 0 || dly2 < 3);
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assert property (@(posedge clk) $fell_gclk(dly1) || dly1 % 2 == 1 || dly2 < 3);
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assert property (@(posedge clk) $past_gclk(dly1) == dly2 || dly2 < 3);
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assert property (@(posedge clk) !$stable_gclk(dly2) || dly2 < 3);
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assert property (@(posedge clk) $changed_gclk(dly2) || dly2 < 3);
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// global_clocking_future_functions are not supported yet:
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// $changing_gclk global_clocking_future_function
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// $falling_gclk global_clocking_future_function
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// $future_gclk global_clocking_future_function
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// $rising_gclk global_clocking_future_function
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// $steady_gclk global_clocking_future_function
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endmodule
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module Test2 ( /*AUTOARG*/
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// Inputs
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clk,
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in
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);
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input clk;
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input [31:0] in;
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bit [31:0] dly0 = 0;
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bit [31:0] dly1 = 0;
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bit [31:0] dly2 = 0;
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= dly0;
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dly2 <= dly1;
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if ($rose(dly0[31:4])) $stop;
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if ($fell(dly1[31:4])) $stop;
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if (!$stable(dly2[31:4])) $stop;
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if ($changed(dly2[31:4])) $stop;
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end
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default clocking @(posedge clk);
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endclocking
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assert property ($rose(dly0[0]) || dly0 % 2 == 0 || dly2 < 3);
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assert property ($fell(dly1[0]) || dly1 % 2 == 1 || dly2 < 3);
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assert property ($stable(dly2[31:4]) || dly2 < 3);
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assert property (!$changed(dly2[31:4]) || dly2 < 3);
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endmodule
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module Test3 ( /*AUTOARG*/
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// Inputs
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clk,
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in
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);
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input clk;
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input [31:0] in;
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// Check the named form of global clocking
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global clocking gck @(posedge clk);
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endclocking
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endmodule
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