45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Regression for prelim ASCRANGE on cfg-based interface typedefs
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package axis;
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typedef struct packed {int unsigned DataWidth;} cfg_t;
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endpackage
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interface axis_if #(
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parameter axis::cfg_t cfg = '0
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) ();
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typedef logic [cfg.DataWidth-1:0] tdata_t;
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endinterface
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module axis_chan #(
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parameter axis::cfg_t chan_cfg = '0
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) ();
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axis_if #(chan_cfg) axis_channel_io ();
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typedef axis_channel_io.tdata_t data_t;
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localparam int kWidth = $bits(data_t);
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initial begin
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#1;
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`checkd(kWidth, 32);
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end
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endmodule
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module t;
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localparam axis::cfg_t axis_chan_cfg = '{DataWidth: 32};
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axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan ();
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initial begin
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#2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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