19 lines
382 B
Systemverilog
19 lines
382 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// See issue #1991
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module t #(
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parameter [96:0] P = 97'h12344321_12344321_12344327
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) (
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input [P&7 - 1:0] in,
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output [P&7 - 1:0] out
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);
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assign out = in;
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endmodule
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