28 lines
604 B
Systemverilog
28 lines
604 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Ian Thompson
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// SPDX-License-Identifier: CC0-1.0
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//bug1099
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typedef struct packed {logic foo;} some_struct_t;
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module child ();
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logic a_bad;
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// bar is in the parent module, but illegal to reference without module name
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assign a_bad = bar.foo;
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endmodule
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module parent #(
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parameter PARAM = 0
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) ();
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some_struct_t bar;
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child c ();
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endmodule
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module t;
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// The parameter must be anything other than the default
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parent #(1) p ();
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endmodule
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