19 lines
439 B
Systemverilog
19 lines
439 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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string S = "<unset>"
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);
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initial begin
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$value$plusargs("S=%s", S); // BAD assignment to S
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#1; // Original bug got compile time error only with this line
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$display("S=%s", S);
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$finish;
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end
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endmodule
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