150 lines
3.8 KiB
Systemverilog
150 lines
3.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg reset;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire myevent; // From test of Test.v
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wire myevent_pending; // From test of Test.v
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wire [1:0] state; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.state(state[1:0]),
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.myevent(myevent),
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.myevent_pending(myevent_pending),
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// Inputs
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.clk(clk),
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.reset(reset)
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, myevent_pending, myevent, state};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent,
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myevent_pending);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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reset <= (cyc < 2);
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4e93a74bd97b25ef
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Outputs
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state,
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myevent,
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myevent_pending,
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// Inputs
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clk,
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reset
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);
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input clk;
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input reset;
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output [1:0] state;
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output myevent;
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output myevent_pending;
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reg [5:0] count = 0;
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always @(posedge clk)
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if (reset) count <= 0;
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else count <= count + 1;
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reg myevent = 1'b0;
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always @(posedge clk) myevent <= (count == 6'd27);
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reg myevent_done;
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reg hickup_ready;
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reg hickup_done;
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localparam STATE_ZERO = 0;
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localparam STATE_ONE = 1;
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localparam STATE_TWO = 2;
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reg [1:0] state = STATE_ZERO;
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reg state_start_myevent = 1'b0;
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reg state_start_hickup = 1'b0;
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reg myevent_pending = 1'b0;
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always @(posedge clk) begin
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state <= state;
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myevent_pending <= myevent_pending || myevent;
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state_start_myevent <= 1'b0;
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state_start_hickup <= 1'b0;
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case (state)
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STATE_ZERO:
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if (myevent_pending) begin
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state <= STATE_ONE;
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myevent_pending <= 1'b0;
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state_start_myevent <= 1'b1;
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end
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else if (hickup_ready) begin
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state <= STATE_TWO;
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state_start_hickup <= 1'b1;
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end
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STATE_ONE: if (myevent_done) state <= STATE_ZERO;
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STATE_TWO: if (hickup_done) state <= STATE_ZERO;
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default: ; /* do nothing */
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endcase
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end
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reg [3:0] myevent_count = 0;
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always @(posedge clk)
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if (state_start_myevent) myevent_count <= 9;
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else if (myevent_count > 0) myevent_count <= myevent_count - 1;
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initial myevent_done = 1'b0;
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always @(posedge clk) myevent_done <= (myevent_count == 0);
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reg [4:0] hickup_backlog = 2;
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always @(posedge clk)
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if (state_start_myevent) hickup_backlog <= hickup_backlog - 1;
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else if (state_start_hickup) hickup_backlog <= hickup_backlog + 1;
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initial hickup_ready = 1'b1;
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always @(posedge clk) hickup_ready <= (hickup_backlog < 3);
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reg [3:0] hickup_count = 0;
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always @(posedge clk)
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if (state_start_hickup) hickup_count <= 10;
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else if (hickup_count > 0) hickup_count <= hickup_count - 1;
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initial hickup_done = 1'b0;
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always @(posedge clk) hickup_done <= (hickup_count == 1);
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endmodule
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