38 lines
991 B
Systemverilog
38 lines
991 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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function automatic int one();
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return 1;
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endfunction
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function automatic int two();
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/* verilator no_inline_task */
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return 2;
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endfunction
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class C;
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static int i = one() + 1;
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static int j = two() + 1;
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endclass
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initial begin
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`checkh(C::i, 2);
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`checkh(C::j, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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