22 lines
579 B
Systemverilog
22 lines
579 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`ifdef VERILATOR
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// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
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`define IMPURE_ONE $c(1)
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`else
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// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
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`define IMPURE_ONE |($random | $random)
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`endif
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module t;
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initial begin
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$write("%f\n", `IMPURE_ONE ? 1.234 : 1.234);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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