verilator/test_regress/t/t_net_delay.out

38 lines
2.2 KiB
Plaintext

%Warning-STMTDLY: t/t_net_delay.v:18:10: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
18 | always #2 clk = ~clk;
| ^
... For warning description see https://verilator.org/warn/STMTDLY?v=latest
... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: t/t_net_delay.v:24:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
24 | wire [3:0] #3 val1;
| ^
%Warning-STMTDLY: t/t_net_delay.v:25:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
25 | wire [3:0] #3 val2;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:26:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
26 | wire [3:0] #5 val3 = cyc;
| ^
... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: t/t_net_delay.v:27:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
27 | wire [3:0] #5 val4;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:28:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
28 | wire [3:0] #3 val5 = x, val6 = cyc;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:31:10: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
31 | assign #3 val2 = cyc;
| ^
%Warning-STMTDLY: t/t_net_delay.v:44:5: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
44 | #1 begin
| ^
%Error: Exiting due to