46 lines
1.3 KiB
Systemverilog
46 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// MULTIDRIVEN false positive - package function return var
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//
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// Minimal reproducer for: package function with "return expr" used in always_comb expression.
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// The function return variable must not be treated as a side-effect "writeSummary" target.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package p;
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function automatic int num_bytes(input int size);
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return 1 << size;
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endfunction
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endpackage
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module t;
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typedef struct packed {
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logic [31:0] addr;
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logic [2:0] size;
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} meta_t;
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meta_t rd_meta_q;
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meta_t rd_meta;
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always_comb begin
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rd_meta = rd_meta_q;
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rd_meta.addr = rd_meta_q.addr + p::num_bytes(int'(rd_meta_q.size));
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end
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initial begin
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rd_meta_q.addr = 32'h100;
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rd_meta_q.size = 3'd2; // num_bytes = 4
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#1;
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`checkd(rd_meta.addr, 32'h104);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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