41 lines
837 B
Systemverilog
41 lines
837 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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/* verilator lint_off WIDTH */
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integer cyc;
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initial cyc = 0;
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logic [31:0] arr_c;
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initial arr_c = 0;
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logic [7:0][3:0] arr;
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logic [31:0] arr2_c;
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initial arr2_c = 0;
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logic [7:0][3:0] arr2;
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assign arr2_c = arr2;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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arr_c <= arr_c + 1;
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arr2 <= arr2 + 1;
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`ifdef TEST_VERBOSE
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$write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2],
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arr[3]);
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`endif
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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/* verilator lint_on WIDTH */
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endmodule
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