93 lines
1.9 KiB
Systemverilog
93 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// verilator lint_off ASCRANGE
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wire [7:0] array[2:0][1:3];
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wire [7:0] arrayNoColon[2][3];
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// verilator lint_on ASCRANGE
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integer cyc;
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initial cyc = 0;
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integer i0, i1, i2;
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genvar g0, g1, g2;
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generate
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for (g0 = 0; g0 < 3; g0 = g0 + 1) begin
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for (g1 = 1; g1 < 4; g1 = g1 + 1) begin
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inst inst (
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.q(array[g0[1:0]][g1[1:0]]),
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.cyc(cyc),
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.i0(g0[1:0]),
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.i1(g1[1:0])
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);
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end
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end
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endgenerate
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always @(posedge clk) begin
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//$write("cyc==%0d\n",cyc);
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cyc <= cyc + 1;
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if (cyc == 2) begin
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if (array[2][1] !== 8'h92) $stop;
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for (i0 = 0; i0 < 3; i0 = i0 + 1) begin
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for (i1 = 1; i1 < 4; i1 = i1 + 1) begin
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//$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]);
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if (array[i0[1:0]][i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop;
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end
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end
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end
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else if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module inst ( /*AUTOARG*/
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// Outputs
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q,
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// Inputs
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cyc,
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i0,
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i1
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);
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output reg [7:0] q;
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input [31:0] cyc;
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input [1:0] i0;
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input [1:0] i1;
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inst2 inst2 ( /*AUTOINST*/
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// Inputs
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.cyc(cyc[31:0]),
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.i0(i0[1:0]),
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.i1(i1[1:0])
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);
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always @* begin
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q = {i0, i1, cyc[3:0]};
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end
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endmodule
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module inst2 ( /*AUTOARG*/
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// Inputs
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cyc,
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i0,
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i1
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);
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/*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining
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input [31:0] cyc;
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input [1:0] i0;
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input [1:0] i1;
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initial begin
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if (cyc == 32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1);
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end
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endmodule
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