34 lines
525 B
Systemverilog
34 lines
525 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2006 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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b,
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// Inputs
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clk,
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en,
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a
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);
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// bug1017
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input clk;
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input en;
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input a[1];
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output logic b[1];
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always_ff @(posedge clk) begin
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b <= en ? a : b;
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end
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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