26 lines
518 B
Systemverilog
26 lines
518 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Jie Xu
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [1:0][31:0] tt;
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] c;
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initial begin
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a = 1;
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b = 2;
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c = 3;
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tt[0] = a;
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tt[1] = b;
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tt[2] = c; // Out of bounds
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if (tt[0] != a) $stop;
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if (tt[1] != b) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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