72 lines
1.6 KiB
Systemverilog
72 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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logic hugemem[257];
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initial hugemem = '{default: 1'b0};
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// [16] is SV syntax for [0:15]
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reg [7:0] memory8_16[16];
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reg m_we;
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reg [3:1] m_addr;
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reg [15:0] m_data;
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always @(posedge clk) begin
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// Load instructions from cache
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memory8_16[{m_addr, 1'd0}] <= 8'hfe;
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if (m_we) begin
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{memory8_16[{m_addr, 1'd1}], memory8_16[{m_addr, 1'd0}]} <= m_data;
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end
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end
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reg [7:0] memory8_16_4;
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reg [7:0] memory8_16_5;
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// Test complicated sensitivity lists
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always @(memory8_16[4][7:1] or memory8_16[5]) begin
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memory8_16_4 = memory8_16[4];
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memory8_16_5 = memory8_16[5];
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end
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always @(posedge clk) begin
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m_we <= 0;
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$display(hugemem);
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m_we <= 1'b1;
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m_addr <= 3'd2;
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m_data <= 16'h55_44;
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end
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if (cyc == 2) begin
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m_we <= 1'b1;
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m_addr <= 3'd3;
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m_data <= 16'h77_66;
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end
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if (cyc == 3) begin
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m_we <= 0; // Check we really don't write this
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m_addr <= 3'd3;
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m_data <= 16'h0bad;
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end
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if (cyc == 5) begin
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if (memory8_16_4 != 8'h44) $stop;
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if (memory8_16_5 != 8'h55) $stop;
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if (memory8_16[6] != 8'hfe) $stop;
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if (memory8_16[7] != 8'h77) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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