88 lines
2.4 KiB
Systemverilog
88 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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input clk
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);
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integer i;
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reg [6:0] w7;
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reg [14:0] w15;
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reg [30:0] w31;
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reg [62:0] w63;
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reg [94:0] w95;
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integer cyc = 0;
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d\n", $time, cyc);
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`endif
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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w7 = {7{1'b1}};
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w15 = {15{1'b1}};
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w31 = {31{1'b1}};
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w63 = {63{1'b1}};
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w95 = {95{1'b1}};
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end
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else if (cyc == 1) begin
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if (w7++ != {7{1'b1}}) $stop;
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if (w7 != {7{1'b0}}) $stop;
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if (w7-- != {7{1'b0}}) $stop;
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if (w7 != {7{1'b1}}) $stop;
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if (++w7 != {7{1'b0}}) $stop;
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if (w7 != {7{1'b0}}) $stop;
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if (--w7 != {7{1'b1}}) $stop;
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if (w7 != {7{1'b1}}) $stop;
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if (w15++ != {15{1'b1}}) $stop;
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if (w15 != {15{1'b0}}) $stop;
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if (w15-- != {15{1'b0}}) $stop;
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if (w15 != {15{1'b1}}) $stop;
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if (++w15 != {15{1'b0}}) $stop;
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if (w15 != {15{1'b0}}) $stop;
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if (--w15 != {15{1'b1}}) $stop;
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if (w15 != {15{1'b1}}) $stop;
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if (w31++ != {31{1'b1}}) $stop;
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if (w31 != {31{1'b0}}) $stop;
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if (w31-- != {31{1'b0}}) $stop;
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if (w31 != {31{1'b1}}) $stop;
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if (++w31 != {31{1'b0}}) $stop;
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if (w31 != {31{1'b0}}) $stop;
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if (--w31 != {31{1'b1}}) $stop;
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if (w31 != {31{1'b1}}) $stop;
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if (w63++ != {63{1'b1}}) $stop;
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if (w63 != {63{1'b0}}) $stop;
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if (w63-- != {63{1'b0}}) $stop;
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if (w63 != {63{1'b1}}) $stop;
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if (++w63 != {63{1'b0}}) $stop;
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if (w63 != {63{1'b0}}) $stop;
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if (--w63 != {63{1'b1}}) $stop;
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if (w63 != {63{1'b1}}) $stop;
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if (w95++ != {95{1'b1}}) $stop;
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if (w95 != {95{1'b0}}) $stop;
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if (w95-- != {95{1'b0}}) $stop;
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if (w95 != {95{1'b1}}) $stop;
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if (++w95 != {95{1'b0}}) $stop;
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if (w95 != {95{1'b0}}) $stop;
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if (--w95 != {95{1'b1}}) $stop;
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if (w95 != {95{1'b1}}) $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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