40 lines
950 B
Systemverilog
40 lines
950 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2006 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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// New number format
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if ('0 !== {66{1'b0}}) $stop;
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if ('1 !== {66{1'b1}}) $stop;
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if ('x !== {66{1'bx}}) $stop;
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if ('z !== {66{1'bz}}) $stop;
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`ifndef NC // NC-Verilog 5.50-s09 chokes on this test
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if ("\v" != 8'd11) $stop;
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if ("\f" != 8'd12) $stop;
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if ("\a" != 8'd7) $stop;
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if ("\x9a" != 8'h9a) $stop;
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if ("\xf1" != 8'hf1) $stop;
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`endif
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end
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if (cyc == 8) begin
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end
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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