72 lines
1.4 KiB
Systemverilog
72 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Clifford Wolf
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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wire [31:0] y;
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reg a;
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test004 sub ( /*AUTOINST*/
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// Outputs
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.y(y[31:0]),
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// Inputs
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.a(a)
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);
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y);
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`endif
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cyc <= cyc + 1;
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if (cyc == 0) begin
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a <= 0;
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end
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else if (cyc == 1) begin
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a <= 1;
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if (y != 32'h0) $stop;
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end
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else if (cyc == 2) begin
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if (y != 32'h010000ff) $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module test004 (
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a,
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y
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);
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input a;
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output [31:0] y;
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wire [7:0] y0;
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wire [7:0] y1;
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wire [7:0] y2;
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wire [7:0] y3;
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assign y = {y0, y1, y2, y3};
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localparam [7:0] V0 = +8'sd1 ** -8'sd2; //'h01
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localparam [7:0] V1 = +8'sd2 ** -8'sd2; //'h00
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localparam [7:0] V2 = -8'sd2 ** -8'sd3; //'h00
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localparam [7:0] V3 = -8'sd1 ** -8'sd3; //'hff
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localparam [7:0] ZERO = 0;
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initial $display("V0=%x V1=%x V2=%x V3=%x", V0, V1, V2, V3);
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assign y0 = a ? V0 : ZERO;
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assign y1 = a ? V1 : ZERO;
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assign y2 = a ? V2 : ZERO;
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assign y3 = a ? V3 : ZERO;
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endmodule
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